When known counter circuits are implemented to count numbers having a large number of digits, a tradeoff between circuit area and speed of operation is encountered. A common technique used to implement an electronic count function is to use a prescaler circuit and multiple stages of binary counters which propagate a carry chain. A disadvantage with a separate carry chain in a counter is that for every clock cycle, the carry bit must be propagated from the LSB to the MSB before the counter stages can be toggled again. The stated disadvantage exists for both loading the counter with an initial count value as well as in incrementing or decrementing. To solve the speed problem, a parallel architecture may be implemented which increases both the amount of circuitry and layout routing. Accordingly, a choice between size and speed is required when using counters with numbers having large bit widths.